1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a configuration of a memory cell array and a row decoder in a ROM having a hierarchical bit line architecture.
2. Description of the Related Art
A hierarchical bit line architecture has been proposed for conventional nonvolatile memories, e.g., a FLASH-EEPROM and a mask ROM, (see Japanese Laid-Open Publication No. 6-104406).
FIG. 3A illustrates part of a layout pattern of a conventional semiconductor memory device having a hierarchical bit line architecture. FIG. 3B illustrates part of an equivalent circuit of the conventional semiconductor memory device having a hierarchical bit line architecture shown in FIG. 3A. The semiconductor memory device having a hierarchical bit line architecture is provided on a semiconductor substrate The semiconductor memory device includes a plurality of main bit lines MB1-MB4, . . . ; a plurality of sub bit lines SB11, . . . , SB28, . . . ; a plurality of word lines WL001, . . . , WL232, . . . ; a plurality of memory cell transistors M1-M7, . . . (hereinafter referred to as "memory cells"); a plurality of contacts CT11, . . . , CT22, . . . ; a plurality of auxiliary conductive regions BB11, . . . , BB22, . . . ; a plurality of bank select transistors TB01, . . . , TB27, . . . (hereinafter referred to as "bank cells"); and a plurality of bank select lines BS01, . . . , BS24, . . .
The sub bit lines SB are formed from a diffusion layer of a conductivity type opposite to that of the semiconductor substrate. The word lines WL are provided across the sub bit lines SB and made from polysilicon. Each memory cell M is provided between a pair of adjacent sub bit lines SB. A word line WL is connected to gate electrodes of the memory cells M. Each auxiliary conductive region BB is provided at an end of the sub bit line SB and has the same conductivity type as that of the sub bit line SB. Each bank cell TB is provided between an auxiliary conductive region BB and a sub bit line SB. Each bank select line BS is connected to a gate electrode of a bank cell TB and is made from polysilicon.
The auxiliary conductive regions BB are connected via contacts CT to a main bit line MB. The main bit lines MB are made from a metal. The semiconductor memory device is divided into a plurality of banks BNK0-BNK2, . . . In each bank BNK, an array of the sub bit lines SB are arranged parallel to each other and a set of the auxiliary conductive regions BB are connected to the sub bit lines SB. A number of the bank select lines BS are provided to a bank BNK. A plurality of the banks BNK are provided along the column direction to form a memory cell array. Adjacent banks BNK share a set of the auxiliary conductive regions BB.
In a bank BNK, the sub bit lines SB are arranged in columns. Of adjacent sub bit lines SB, one sub bit line SB is connected via a bank cell TB to a first main bit line MB at one end of the sub bit line SB while the other sub bit line SB is connected via another bank cell TB to a second main bit line MB at the other end of the other sub bit line SB.
The operation of the semiconductor memory device will be described below. In the following description, it is assumed that the semiconductor substrate is of a P-negative type while the sub bit lines SB and the auxiliary conductive regions BB are of an N-positive type.
A memory cell M is selected by setting potentials of the bank select lines BS and the word lines WL to a high level.
The threshold voltage of the memory cell M can be set by the amount of boron ions which are implanted into a channel region of the memory cell M which is formed under a gate electrode thereof. The threshold voltage of the memory cell M becomes greater through ion implantation. A given amount of implanted ions would produce such a memory cell M that remains in an OFF-state even when a gate potential of the memory cell M is at a high level (OFF-cell). The memory cell M without ion implantation can transition to an ON-state when the gate potential is at a high level (ON-cell).
In a similar way, a portion of the bank select line BS which does not form a bank cell TB is subjected to boron ion implantation so as to be permanently in the OFF-state.
A memory cell M in a bank BNK is selected by a row select circuit 202 driving a word line WL that is connected to a gate electrode of the memory cell M to a high level while driving the associated bank select lines BS that are connected to gate electrodes of the associated bank cells TB connected to the sub bit lines SB which are source and drain regions of the memory cell M to a high level. For instance, the memory cell M2 shown shaded in FIGS. 3A and 3B is read out by selecting the bank cells TB11 and TB16. The bank cells TB11 and TB16 are selected by driving the word line WL132 and the bank select lines BS11 and BS14 to a high level and leaving other bit select lines at a low level. When the bank cell TB11 is selected by the high-level bank select line BS11, the sub bit line SB12 becomes electrically connected via the contact CT11 to the main bit line MB2. When the bank cell TB16 is selected by the high-level bank select line BS14, the sub bit line SB13 becomes electrically connected via the contact CT21 to the main bit line MB1.
As described above, the memory cell M2 is selected by activating the word line WL132 and the bank select lines BS11 and BS14 provided on the bank BNK1 including the memory cell M2.
Each of the main bit lines MB are selectively connected to data lines (not shown) by a column select circuit 201. The data content of the selected memory cell M is read out through a route provided by the connection of the data line and main bit line MB.
The two main bit lines MB1 and MB2 are connected via the column select circuit 201 to the data lines. One of the data lines is connected to a low potential while the other of the data lines is connected to a high potential. A state of the memory cell M2 is read out as binary information by detecting a difference in current between the data lines. When the memory cell M2 is an OFF-cell, the other data line remains at the high potential. On the other hand, when the memory cell M2 is an ON-cell, the other data line makes a transition from a high to a low potential. The presence of a transition determines the binary information of the memory cell M2.
By introducing a hierarchical bit line architecture to the memory, the following effect is obtained. Of the plurality of the sub bit lines SB connected to one main bit line MB, only the sub bit lines SB connected to one memory cell M which is a target to be accessed are selected by the bank select lines BS. As a result, a load of the main bit line MB is reduced, thereby realizing high-speed access.
In the above-described nonvolatile memory, a single memory cell M includes one transistor, so that a density of memory cells M is high compared with that of a volatile memory such as a DRAM. However, the wiring pitch of the word lines WL is very small and therefore it is difficult to provide a row decoder and a driving circuit for each word line WL. To solve this problem, a plurality of banks BNK share a group of row decoders and driving circuits. In other words, consecutive plural banks BNK are connected to the same group of row decoders and driving circuits via a common group of word lines WL. Accordingly, the word lines WL each corresponding to an identical row in each of the consecutive plural banks BNK are provided with the same signal and activated simultaneously. To read out an intended memory cell M, it is necessary to activate the bank select lines BS in the bank BNK including the intended memory cell M of the plural banks BNK so as to connect the main bit lines MB to the intended memory cell.
FIG. 3C illustrates a configuration of a conventional semiconductor memory device. Memory cell arrays 11 and 12 are provided on opposite sides of the row select circuit 202. The row select circuit 202 includes a row decoder 30 with a driver 21 and a driver 22 disposed on the right and left sides thereof, respectively. The driver 21 is a circuit for driving a memory cell 11 at the right side thereof while the driver 22 is a circuit for driving a memory cell 12 at the left side thereof.
The row decoder 30 generates a signal to be sent through the bank select line or word line in accordance with an input address signal. The row decoder 30 includes decoders RB1AU, RB1AL, . . . which create states of bank select lines BS1AU, BS1AL, . . . in accordance with the address signals; and decoders RW101, RW103, . . . which create states of word lines WL1A01, WL1A02, . . . in accordance with the address signals.
The memory cell array 11 includes banks BNK1A-BNK4B, . . . arrayed along a column direction. A group of the word lines WL which are connected to a bank BNK is called a word line group. In FIG. 3C, the word lines WL1A01, . . . , WL1B02, . . . of the banks BNK1A and BNK2A belong to the same word line group since their word line groups are connected to the same set of decoders RW101-RW104. Therefore, the same signal is supplied to the word lines WL1A01 and WL1BO1. When the word lines WL1A01 and WL1B01 are activated, either a pair of the bank select lines BS1AU and BS1AL or a pair of the bank select lines BS1BU and BS1BL will be activated to select either the bank BNK1A or the bank BNK1B. When the bank select lines BS1AU and BS1AL are activated, the word line WL1A01 can select a memory cell M in the bank BNK1A and then the memory cell M in the bank BNK1A is read out. When the bank select lines BS1BU and BS1BL are activated, the word line WL1B01 can select a memory cell M in the bank BNK1B and then the memory cell M in the bank BNK1B is read out.
Furthermore, it is considered to attempt to widen a wiring pitch of the main bit lines MB in the conventional semiconductor memory device having a hierarchical bit line architecture. To this end, the number of the main bit lines MB is decreased while the number of the sub bit lines SB connected to one main bit line MB may be increased. This leads to a problem that the number of the bank select lines BS increases and therefore a chip size becomes greater.
FIG. 3D illustrates part of another layout pattern of a conventional semiconductor memory device. FIG. 3E illustrates part of an equivalent circuit of the conventional semiconductor memory device shown in FIG. 3D. The same components as those in FIGS. 3A and 3B are indicated by the same reference numerals as those used therein. In FIGS. 3D and 3E, four sub bit lines SB are connected to one main bit line MB. In this case, each bank BNK needs eight bank select lines BS as compared with the four bank select lines BS in each bank BNK of FIG. 3C. Therefore, an increased number of the sub bit lines SB connected to one main bit line MB require an increased number of the bank select lines BS, resulting in a larger chip size.
On the other hand, when the consecutive banks BNK share some bank select lines BS, the number of bank select lines BS can be decreased, thereby making it possible to reduce chip size.
FIG. 3F illustrates part of a layout pattern of a semiconductor memory device in which four sub bit lines SB are connected to one main bit line MB and adjacent banks BNK share bank select lines BS. FIG. 3G illustrates an equivalent circuit of the semiconductor memory device shown in FIG. 3F. The same components as those in FIGS. 3A and 3B are indicated by the same reference numerals as those used therein. In this case, as compared with the semiconductor memory device shown in FIGS. 3D and 3E, the number of bank select lines is decreased, thereby reducing chip size.
In FIGS. 3F and 3G, however, bank cells TB (e.g., TB17 and TB27) in adjacent banks (e.g., BNK1 and BNK2) are simultaneously selected since these bank cells TB share the same bank select line BS (e.g., BS14) that is connected to the gates electrodes of the bank cells TB. Therefore, when the same word line group is connected to the adjacent banks BNK, extra two sub bit lines (e.g., SB15 and SB25) are simultaneously connected to one main bit line MB (e.g., MB1) when selecting one bank select line BS (e.g., BS14). Further, when the memory cell M selected by the word line WL is an ON-cell, an undesirable transient current flows in the main bit line MB, resulting in an access delay.
Referring to FIGS. 3F and 3G, a case where a memory cell M4 is read out will be described in greater detail. When a word line WL132 and bank select lines BS12 and BS14 are activated (raised to a high potential), a row including the memory cell M4 and bank cells TB11 and TB17 are selected and sub bit lines SB14 and SB15 are connected via the bank cells TB11 and TB17 to main bit lines MB2 and MB1, respectively. At this time, a bank cell TB27 is selected by the bank select line BS14 while a bank cell TB01 is selected by the bank select line BS12. Therefore, in a bank BNK2, a sub bit line SB25 also is connected via the bank cell TB27 to the main bit line MB1. However, when it is assumed that the adjacent banks BNK1 and BNK2 have the same word line group, a word line WL232 in the bank BNK2 also is activated. Accordingly, when it is further assumed that memory cells M21 and M22 selected by the word line WL232 are ON-cells, sub bit lines SB24 and SB26 are also connected via the memory cells M21 and M22 to the main bit line MB1, constituting a load. Furthermore, when memory cells adjacent to the memory cells M21 and M22 also are ON-cells, sub bit lines SB of the further memory cells M are connected to the main bit line MB1, constituting a load. The charging and discharging of these loads lead to an access delay.